1. Field of the Invention
The present invention relates to the structure of a semiconductor device and a method for preparing the structure, in particular to a trench structure of device isolation region for electrically isolating devices and a method for preparing the trench structure.
2. Background of the Invention
In FIG. 9, there is shown a conventional process for fabricating a semiconductor device which has a device isolation region formed therein. In FIG. 9 is shown the formation of a device isolation region disclosed in JP-A-5259269.
In accordance with the conventional process, a trench is formed so as to have a sidewall bent in a two-stage fashion from a surface of a semiconductor substrate toward a bottom thereof, and then thermal oxidation is carried out to form a device isolation region having a silicon oxide film in the trench.
In the formation of the device isolation according to the conventional method, a silicon oxide film 102 and a silicon nitride film 103 are sequentially deposited on the surface 101a of the semiconductor substrate 101, and a resist pattern 104 which has a window 104a formed therein so as to correspond to a device isolation region forming portion is deposited on the silicon nitride film 103 as shown in FIG. 9(a).
Next, the silicon nitride film 103 is subjected to an anisotropic etching with use of the resist pattern 104 as an etching mask to dig a portion of the silicon nitride film under the window 104a as shown in FIG. 9(b).
Further, the silicon oxide film 102 is etched by RIE (Reactive Ion Etching) with use of the resist pattern 104 as an etching mask to dig a portion of the silicon oxide film under the windows 104a, thereby exposing a portion of the surface 101a of the semiconductor substrate 101 under the window as shown in FIG. 9(c).
The portion of the surface 101a of the semiconductor substrate 101 is continuously subjected to RIE to be digged down, providing a trench 105 having a profile angle 105a as shown in FIG. 9(d). At that time, a fluorocarbon polymer film 106 is simultaneously created and is deposited on a sidewall of the window 104a.
After that, the semiconductor substrate 101 is subjected to isotropic etching with use of the fluorocarbon polymer film 106 as an etching mask to further dig the trench 105, providing a trench 107 having a substantially vertical sidewall as shown in FIG. 9(e).
Next, the resist pattern 104 and the fluorocarbon polymer film 106 are eliminated as shown in FIG. 9(f).
After that, the device isolation region can be formed by providing a silicon oxide film on the trench 107 by thermal oxidation though not shown.
As explained, in the device isolation region formed according to the conventional method, the trench 107 is formed so as to have such a vertical sidewall, and the silicon oxidation film is deposited on the trench by thermal oxidation. As a result, a great deal of stress is applied to a bent portion with a bottom surface and the sidewall of the trench 107 contacting each other, and a defect is caused in the semiconductor substrate 101 by the stress, creating a problem in that device isolation characteristics degrade.
In general, a device isolation region which is provided by a trench in a semiconductor substrate and burying an isolating film in the trench for electrically isolating devices is called trench isolation. The formation of the trench isolation has a problem in that an edge portion suffers from a inverse narrow channel effect wherein the subthreshold characteristics of a transistor formed near to the trench isolation is adversely affected by a parasitic MOS transistor and wherein the threshold voltage of the transistor lowers as the size of the channel width is reduced. This is because the presence of a steep angle at a trench edge near to the surface of the substrate having the silicon oxide film for the device isolation with the substantially vertical sidewall causes an electric field from a gate electrode to concentrate on the trench edge when a voltage is applied to the gate electrode.
In addition, there is created a problem in that the oxidation of a surface of the device isolation region and the oxidation of a surface of an active region around it are different from each other in terms of oxidation rate, and an oxidation film which is formed on the active region and required for formation of a gate oxidation film as a constituent element of a MOS transistor is made into a thin film.
The device isolation region has to be buried at a position deeper than a predetermined depth in order to ensure required device isolation characteristics.
In the fabrication, the trench 107 is formed so as to have the stepwise sidewall by etching under two kinds of different conditions with use of the single etching mask. In the etching wherein the fluorocarbon polymer film 106 is created and deposited on the sidewall of the etching mask, the fluorocarbon polymer film 106 deposited on the sidewall peels at random during the etching, and some of a plurality trenches finally formed in a single substrate have uneven shapes, creating a problem in that devices formed around the device isolation region are adversely affected in terms of electrical sense.